As is known, a nonvolatile memory device comprises a memory array formed by memory cells arranged in rows and columns, wherein wordlines connect gate terminals of memory cells on the same row, and bitlines connect drain terminals of memory cells on the same column.
Individual rows of the memory array are addressed by a row decoder receiving an encoded address and biasing the wordline of the row each time addressed at a stable and precise voltage, the value of which depends upon the type of operation to be carried out (reading, programming, verifying, erasing), whilst individual columns of the memory array are addressed by a column decoder receiving the same encoded address and biasing the bitline of the column each time addressed at a voltage such as to guarantee that on the drain terminal of the addressed memory cell there is a pre-set electrical potential, which often must be precise, stable, and controlled.
It is also known that in a floating-gate nonvolatile memory cell, storage of a logic value is performed by programming the threshold voltage of the memory cell through the injection of an appropriate amount of electrical charge in the floating-gate region.
According to the information stored, the memory cells are distinguished into erased memory cells (logic value stored “1”), in the floating-gate region of which no electrical charge is stored, and written or programmed memory cells (logic value stored “0”), in the floating-gate region of which an electrical charge is stored that is sufficient to cause an increase in the threshold voltage of the memory cells, the increase being large enough to be sensed.
The most widely used method for reading nonvolatile memory cells envisages comparing a quantity correlated to the current flowing through the array memory cell with a similar quantity correlated to the current flowing through a reference memory cell with known contents.
In particular, to carry out reading of an array memory cell, a read voltage having a value between the threshold voltage of an erased memory cell and that of a written memory cell is supplied to the gate terminal of the memory cell, in such a way that, if the array memory cell is written, the read voltage is lower than its threshold voltage, and hence current does not flow in the array memory cell, whilst, if the memory cell is erased, the read voltage is higher than its threshold voltage, and hence a current flows in the array memory cell.
The reading of an array memory cell is performed by a reading circuit generally known as sense amplifier, which is connected to the bitlines and, in addition to recognition of the logic value stored in the array memory cell to be read, also provides for the correct biasing of the drain terminal of the array memory cell.
A general circuit architecture of a nonvolatile memory device of the type described above is schematically shown in FIG. 1, wherein 1 designates the memory device as a whole, 2 designates the memory array, 3 designates the row decoder, 4 designates the column decoder, 5 designates the reading circuit, and 6 designates a supply stage connected to the row and column decoders 3, 4 and supplying biasing voltages for the wordlines and bitlines of the memory array 2, which are necessary during the various operating steps of the memory device (reading, writing, and erasing).
A common drawback in the memory devices of the type described above is represented by the fact that biasing of a memory cell during reading induces in the memory cell an electrical stress that takes the form of a loss and/or a gain of electrical charge stored in the floating-gate region, with the risk of altering the logic value stored therein.
This danger is particularly felt in the reference memory cell, which is in fact addressed at each reading of the memory array, and consequently an alteration of the electrical charge stored therein could have catastrophic consequences on the reading of the memory array.
The solution currently adopted for overcoming this drawback consists of using a number of reference memory cells, each of which is used during reading of a corresponding portion of the memory array. In this way, the electrical stress induced by biasing is uniformly distributed over the various reference memory cells, and hence each reference memory cell is subjected to an electrical stress reduced by a factor equal to the number of reference memory cells.
As compared to the solution with a single reference memory cell, the solution with a number of reference memory cells involves, on the one hand, a noticeable increase in the occupation of area on the silicon, and, on the other hand, an increase in the programming times of the reference memory cells.
This drawback is then further accentuated in that in actual fact, each reference is not constituted by a single memory cell, but rather by a bank of memory cells arranged in rows and columns, in which just one of the memory cells actually performs the task of reference element during reading, whilst the other memory cells that surround it have only the purpose of reproducing the same environment that surrounds the array memory cell to be read so that its physical structure will become as much as possible similar to that of the array memory cell, thus reducing behavioral differences that can be attributed to lithographic aspects of the process.